The present invention is directed to semiconductor devices and, more specifically, to thyristor-based devices including thyristor-based memory devices.
Recent technological advances in the semiconductor industry have permitted dramatic increases in integrated circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Presently, single-die microprocessors are being manufactured with many millions of transistors, operating at speeds of hundreds of millions of instructions per second and being packaged in relatively small, air-cooled semiconductor device packages. The improvements in such devices have led to a dramatic increase in their use in a variety of applications. As the use of these devices has become more prevalent, the demand for reliable and affordable semiconductor devices has also increased. Accordingly, the need to manufacture such devices in an efficient and reliable manner has become increasingly important.
An important part in the circuit design, construction, and manufacture of semiconductor devices concerns semiconductor memory and other circuitry used to store information. Conventional random access memory devices include a variety of circuits, such as SRAM and DRAM circuits. The construction and formation of such memory circuitry typically involves forming at least one storage element and circuitry designed to access the stored information. DRAM is very common due to its high density (e.g., high density has benefits including low price). DRAM cell size is typically between 6 F2 and 8 F2, where F is the minimum feature size. However, with typical DRAM access times of approximately 50 nSec, DRAM is relatively slow compared to typical microprocessor speeds and requires refresh. SRAM is another common semiconductor memory that is much faster than DRAM and, in some instances, is of an order of magnitude faster than DRAM. Also, unlike DRAM, SRAM does not require refresh. SRAM cells are typically constructed using 4 transistors and 2 resistors or 6 transistors, which result in much lower density and is typically between about 60 F2 and 100 F2.
Various SRAM cell designs based on a NDR (Negative Differential Resistance) construction have been introduced, ranging from a simple bipolar transistor to complicated quantum-effect devices. These cell designs usually consist of at least two active elements, including an NDR device. In view of size considerations, the construction of the NDR device is important to the overall performance of this type of SRAM cell. One advantage of the NDR-based cell is the potential of having a cell area smaller than four-transistor and six-transistor SRAM cells because of the smaller number of active devices and interconnections.
Conventional NDR-based SRAM cells, however, have many problems that have prohibited their use in commercial SRAM products. These problems include, among others: high standby power consumption due to the large current needed in one or both of the stable states of the cell; excessively high or excessively low voltage levels needed for cell operation; stable states that are too sensitive to manufacturing variations and provide poor noise-margins; limitations in access speed due to slow switching from one state to the other; limitations in operability due to temperature, noise, voltage and/or light stability; and manufacturability and yield issues due to complicated fabrication processing.
NDR devices including thyristors are widely used in power switching applications because the current densities carried by such devices can be very high in their on state. The performance of such NDR devices is dependent on many physical and operational parameters, including the interaction of a control port, such as a thyristor gate and the body of the thyristor. For example, it has been discovered that it is generally useful to control voltages to which the thyristor gate is exposed during various operating conditions of the NDR device in a manner that prevents an unwanted conductive channel from being formed in the body of the thyristor. Effectively, the formation of such a channel can result in a parasitic MOSFET being turned on within the thyristor. Controlling the voltages in this manner, however, is limiting in that the voltage for certain applications cannot be optimized where such an optimum voltage does not prevent the formation of the channel.
A thin capacitively-coupled thyristor-type NDR device can be effective in overcoming many previously unresolved problems in a variety of applications. An important consideration in the design of thin capacitively-coupled thyristor devices involves designing the body of the thyristor sufficiently thin, so that the capacitive coupling between a control port and a base region of the device can substantially modulate the potential of the base region. Another important consideration in the design of thin capacitively-coupled thyristors involves preventing the formation of an unwanted conductive channel within the thyristor, as discussed above.
These and other design considerations have presented challenges to the implementation of such thyristors in a variety of circuit applications.
The present invention is directed to a semiconductor device, including those specific examples discussed and incorporated above, that addresses the above-mentioned challenges. The present invention is exemplified in a number of implementations and applications, some of which are summarized below.
According to an example embodiment of the present invention, a semiconductor device includes a thyristor having a control port (e.g., gate electrode) that switches a thyristor between a blocking state and a conducting state while inhibiting parasitic MOS-inversion channel formation. The thyristor includes a plurality of thyristor regions including a first base region adjacent to a first emitter region and a second base region adjacent to a second emitter region, with the first and second base regions being electrically coupled to one another. The control port exhibits a workfunction such that the control port is arranged to capacitively couple a signal to at least one of the plurality of thyristor regions in a manner that controls current in the thyristor while inhibiting the formation of the parasitic MOS-inversion channel. With this approach, it has been discovered that the operation of the semiconductor device can be optimized without necessarily increasing the distance between the thyristor gate and a junction between the base and emitter regions, and while inhibiting the tendency of a parasitic MOS-inversion channel from being turned xe2x80x9con.xe2x80x9d When used in memory applications, voltages applied to the thyristor control port during standby, write and read modes can be selected with a wider range of applicable values without necessarily forming a parasitic MOS-inversion channel.
According to a more particular example embodiment of the present invention, a memory cell includes a thyristor having a gate adapted to switch the thyristor between a blocking state and a conducting state while preventing the formation of an unwanted conductive (inversion) channel in the device. The cell also includes a pass device, such as a MOSFET, having first and second source/drain regions separated by a channel region and a pass gate capacitively coupled to the channel region via a gate dielectric. The pass gate switches the channel region between a blocking state and a conducting state in response to a voltage being applied thereto, and the channel is adapted to electrically couple the first and second source/drain regions when in the conducting state. A bit line is coupled to the first source/drain region and a first word line is coupled to the pass gate. The thyristor has a work function that is different than and defined independent of the work function of the MOS-based pass device.
The thyristor includes a first base region adjacent to a first emitter region and a second base region adjacent to a second emitter region, with the first and second base regions being coupled to one another (e.g., in a PNPN orientation). The first emitter region is connected to the second source/drain region of the pass device. A second word line is coupled to the thyristor gate and is adapted to apply a voltage, such as a standby, read or write voltage, to the control port. In response to the voltage applied by the second word line, the thyristor gate capacitively couples a signal to the first base region that switches the thyristor between blocking and conducting states. The thyristor gate has a workfunction that is adapted to inhibit parasitic MOS-inversion channel formation in the thyristor between the first emitter region and the first base region. In one instance the thyristor gate is arranged to exhibit a workfunction in connection with the first base region such that the threshold voltage that must be applied to the second word line in order to form the parasitic MOS-inversion channel is higher than the actual operating voltage applied to the second word line for selected operation of the memory cell.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and detailed description that follow more particularly exemplify these embodiments.